Branch Delay Instruction

In der Rechnerarchitektur ist eine Branch Delay Instruction ein Maschinenbefehl, der direkt einem bedingtem Verzweigungsbefehl folgt und unabhängig davon, ob die Verzweigung genommen wurde oder nicht, immer ausgeführt wird. Die Position eines solchen Maschinenbefehls in der Pipeline heißt Branch Delay Slot (Warteplatz). Branch Delay Slots können sowohl in verschiedenen RISC-Architekturen wie MIPS, PA-RISC und SPARC als auch in DSP-Architekturen wie µPD77230 und TMS320C3x gefunden werden.


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